The present invention relates to semiconductor devices, and more particularly to a semiconductor integrated circuit (IC) which includes at least one memory cell having a trench capacitor in which the trench walls have been roughened for enhanced capacitance using a metal silicide such as CoSi2 as a roughening agent.
A dynamic memory cell in an IC comprises a transistor and an associated capacitor. The capacitor consists of a pair of conductive plates, i.e., electrodes, which are separated from each other by a node dielectric material. Information or data is stored in the memory cell in the form of charge accumulated on the capacitor. As the density of the ICs with memory cells is increased, the area for the capacitor becomes smaller and the amount of charge the capacitor is able to accumulate is reduced. Thus, with less charge to detect, reading the information or data from the memory cell becomes much more difficult.
With a limited fixed space or volume for the capacitor of a memory cell in a highly integrated circuit, there are three known techniques for increasing the amount of charge within a fixed space or area. These three known techniques include: (1) decreasing the thickness of the dielectric material, i.e., node dielectric, that is located between the capacitor plates; (2) changing the dielectric material to one with a dielectric constant higher than SiO2 or Si3N4; or (3) increasing the surface area of the space to be used for the capacitor. Note that it is possible to use a combination of (1) or (2) with (3).
Of the above-mentioned techniques, solution (3) is the most viable because the other two solutions have drawbacks associated therewith. For example, solution (1), which thins the capacitor dielectric, also increases leakage currents that may affect the memory retention performance of the capacitor and the reliability of the memory cell. Solution (2), which purports to change the dielectric material to a higher-dielectric constant material, will only cause a slight improvement in charge storage because the dielectric constant of suitable alternative dielectrics is only slightly higher than the dielectric material currently being used. Moreover, the substitution of alternative dielectrics may be more complicated, more expensive and provide fabrication problems that are heretofore unknown. Accordingly, solution (3), i.e., increasing the surface area of the space to be used for the capacitor, provides the most promise for substantially improving the amount of charge stored without causing any of the problems mentioned for solutions (1) and (2) above.
One previous solution to increase the surface area of the capacitor is to replace common stack capacitor technology with a trench capacitor. In common stack capacitor technology, the capacitor is built on a surface created on a semiconductor substrate. Whereas in trench capacitor technology, the capacitor is formed within a trench that is formed in a semiconductor substrate itself. An increase in depth of the trench, increases the surface area of the capacitor. However, the depth of the trench is limited by present fabrication methods and tools. This problem is further compounded by the continually increasing density of ICs achieved by dimensional shrinkage. To offset the loss of surface area due to a reduction in width, the depth of the trench must be further increased to the point where the necessary depth is not achievable or becomes prohibitively expensive.
Another prior art method to increase the surface area of the capacitor is to provide capacitor plates that contain textured or roughened surfaces in the deep trench adjacent to the dielectric material. A capacitor plate having roughened surface area increases the amount of surface area of the capacitor due to the peaks and valleys of the roughened surface. With this prior art structure and method, the depth of the trench is maximized and the rough surface of the plates is designed to give maximum surface area based on a cross-section of the roughened surface so that the surface area is three-dimensional at the interface of the plates and the dielectric material. However, this prior art method may result in microscopic roughness with sharp features or peaks on the order of a few Angstroms on the capacitor plate which may give rise to leakage through the dielectric material.
Co-assigned U.S. application Ser. No. 09/559,884, filed Apr. 26, 2000 provides a method of roughening the walls of a deep trench capacitor for increasing the charge storage capability of the trench without current leakage. In that application, oxidizable hemispherical silicon grains (HSG) are employed. When such material is employed in roughening the interior walls of the trench, residual polysilicon may remain on the trench walls therefore allowing current leakage to occur.
Co-assigned U.S. application Ser. No. 09/607,594, filed Jun. 30, 2001 discloses an alternative method of providing a deep trench having roughened trench sidewalls. In this prior disclosure, a discontinuous polysilicon layer is formed on the trench sidewalls instead of the HSG material disclosed above. The discontinuous polysilicon layer has gaps which expose a portion of the Si substrate such that during a subsequent oxidizing step an oxide material forms in the gaps which is smooth and wavy. The oxide material is then etched away so as to form smooth hemispherical grooves on the walls of the deep trench region.
Like the previous method, the discontinuous polysilicon material remains in the structure as a partially polycrystalline material even after the annealing step. Moreover, in both processes, gas phase doping is typically carried out to self-align the buried plate to the roughness before the capacitor dielectric is deposited. The doping profile, is not uniform and less aligned to the roughness in these prior art structures due to the rapid diffusion at the poly-crystalline grain boundaries and also due to the mixture of single and poly-silicon regions.
In view of the above-mentioned drawbacks, there is a need to develop a new and improved method of increasing the surface area of a trench capacitor without causing any substantial current leakage. Moreover, a method of increasing the surface area of a trench capacitor is needed in which the roughened trench walls consists of a single crystalline material; i.e., no polycrystalline material remains after roughening.
One object of the present invention is to provide a method of fabricating a trench for a capacitor in which the surface area of the trench has been increased.
Another object of the present invention is to provide a method of fabricating a trench for a capacitor in which the surface area of the trench is increased without causing any substantial current leakage through the cell.
A further object of the present invention is to provide a method of fabricating a trench for a capacitor in which the roughened trench walls consists of a single crystalline material.
An even further object of the present invention is to provide a method of fabricating a trench for a capacitor having an increased surface area without increasing the depth of the trench.
A yet further object of the present invention is to provide a method of fabricating a trench for a capacitor having increased surface area without increasing the lateral dimension of the trench.
These and other objects and advantages are achieved in the present invention by utilizing a method wherein the increased trench capacitor surface area is obtained by roughening the interior walls (sidewalls and bottom trench wall) of the trench using a metal silicide as a roughening agent.
Specifically, the method of the present invention comprises the steps of:
(a) forming a trench in a Si-containing substrate, said trench having an upper region, a lower region and interior walls including sidewalls which extend to a common bottom wall;
(b) forming a collar region in said upper region of said trench;
(c) forming a metal layer (lumpy or continuous and uniform) on at least a portion of exposed interior walls of said trench;
(d) annealing said metal layer so as to form a metal silicide layer; and
(e) removing said metal silicide layer so as to provide roughened trench walls.
In one embodiment of the present invention, a Si-containing layer is formed atop the metal layer prior to annealing the same. This embodiment is used in circumstances wherein the trench cannot be increased laterally. The term xe2x80x9cSi-containing layerxe2x80x9d includes polysilicon, amorphous Si, SiGe, SiC, or epitaxial Si.
In yet another embodiment of the present invention, a Si-containing layer is formed on the metal silicide layer and thereafter an annealing step is performed which is capable of diffusing the Si-containing layer through the metal silicide layer and causing substantial recrystallization of the diffused Si-containing layer with the Si-containing substrate.
In an even further embodiment of the present invention, silicon germanium (SiGe) or other material that is capable of forming three-dimensional islands on the interior trench walls is formed prior to forming the metal layer (lumpy or continuous and uniform) in the trench.
It should be noted that in the present invention, annealing is typically carried out at a temperature of about 300xc2x0 C. or above, with an annealing temperature from about 500xc2x0 C. or above being more highly preferred. The exact annealing temperature employed will be dependent upon the desired silicide phase to be subsequently formed.